The attacker infers secrets by measuring instantaneous power consumption of target devices, often crypto engines or controllers, and correlating traces with hypothesized internal operations. Simple power analysis (SPA) extracts structure (operation sequences, key-dependent branches); differential/correlation power analysis (DPA/CPA) uses many traces and statistics to recover key bits from tiny data-dependent variations. Practically, measurements may come from instrumented rails during I&T, from a compromised payload monitoring local supplies, or from co-located hardware that senses current/voltage fluctuations. With sufficient traces and alignment (triggering on command/crypto invocation), internal values become observable through their power signatures.
| ID | Name | Tiering | Description | NIST Rev5 | ISO 27001 | Onboard SV | Ground | |
| CM0057 | Tamper Resistant Body | A tamper-resistant physical enclosure increases the effort, time, and equipment required to physically probe, observe, remove, or modify protected spacecraft sensor nodes and embedded components. The enclosure must be designed for the specific physical-access and side-channel threats being addressed and should not be assumed to prevent every invasive or non-invasive attack. A passive tamper-resistant body can provide physical and side-channel protection without continuous processing or electrical power, which may make it suitable for resource-constrained sensor nodes. The design trade must also account for mass, volume, thermal performance, manufacturability, inspection, repairability, qualification, and lifecycle cost. Enclosures incorporating active sensing or response mechanisms require power and must be evaluated separately from fully passive designs. The physical security design must distinguish among tamper resistance, which impedes access; tamper evidence, which leaves observable indications of attempted access; tamper detection, which senses an attempt while it occurs; and tamper response, which protects designated sensitive assets after detection. The required properties and response behavior must be selected according to the protected component, threat model, and mission consequence of both successful tampering and false activation. | PE-19 PE-19(1) PL-8 PL-8(1) SA-3 SA-4(5) SA-4(9) SA-8 SC-51 | A.7.5 A.7.8 A.8.12 A.5.8 A.5.2 A.5.8 A.8.25 A.8.31 A.8.27 A.8.28 | ||||
| CM0058 | Power Randomization | Power randomization is a hardware-level countermeasure against power analysis side-channel attacks, in which an adversary monitors a device's power consumption during cryptographic or other security-sensitive operations to extract secret information such as cryptographic keys by correlating power traces with internal computational states. The technique uses an on-chip hardware mechanism to add data-independent or randomized power activity intended to reduce the observable signal-to-noise ratio between measured power consumption and security-sensitive internal computations. Power randomization increases the number or sophistication of measurements required for power analysis but does not eliminate the underlying leakage or guarantee resistance against averaging, profiling, multi-trace, or higher-order analysis. Power randomization must be incorporated into the chip architecture or selected as an existing capability of the target device. Its implementation can increase dynamic power consumption, die area, thermal load, design and verification complexity, non-recurring engineering cost, and potentially unit fabrication cost. Resulting spacecraft-level mass or volume impacts depend on packaging, power-delivery, and thermal-management consequences. These tradeoffs must be evaluated during the system design phase against the mission's threat model and the availability of alternative or complementary side-channel countermeasures, with power randomization selected where the protection it provides justifies its SWaP and cost impact. | PE-19 PE-19(1) | A.7.5 A.7.8 A.8.12 | ||||
| CM0059 | Power Consumption Obfuscation | Power consumption obfuscation encompasses hardware circuit design techniques and architectural obfuscation strategies that mask the relationship between a device's internal operations and its observable power consumption profile, increasing the difficulty and cost of power analysis side-channel attacks. Unlike power randomization, which adds noise to the power signal, obfuscation techniques actively obscure the underlying power consumption pattern through circuit-level design approaches such as dual-rail logic, balanced circuit topologies, and constant-power execution paths that decouple observable power draw from data-dependent computational activity. These techniques increase manufacturing cost and design complexity for sensor nodes and other embedded hardware, representing a one-time investment at fabrication that must be justified against the mission's physical threat environment and the sensitivity of the data processed by the protected device. Power consumption obfuscation is most effectively applied to hardware executing cryptographic operations or other security-sensitive functions where correlation between power traces and internal state would be most damaging if successfully exploited. | PE-19 PE-19(1) | A.7.5 A.7.8 A.8.12 | ||||