Switching activity in chips, buses, and clocks radiates EM energy that can be captured and analyzed to reveal internal computation. Near-field probes (in test) or proximity receivers (on-orbit assets) can observe harmonics and modulation tied to cipher rounds, key schedules, or protocol framing, sometimes with finer granularity than power analysis. Coupling paths include packages, harnesses, SDR front ends, and poorly shielded enclosures. By training on known operations and comparing spectra or time-domain signatures, an adversary can recover keys or reconstruct processed data without touching logical interfaces.
| ID | Name | Tiering | Description | NIST Rev5 | ISO 27001 | Onboard SV | Ground | |
| CM0003 | TEMPEST / EMSEC | TEMPEST controls (i.e., emissions security (EMSEC)) protect spacecraft system components, internal data communications, and communication buses against side-channel and proximity-based attacks that exploit unintended electromagnetic, electrical, or acoustic emanations. Critical components must be enclosed within appropriate casings or shielding structures that attenuate unintended emissions to levels that deny adversaries the ability to reconstruct processed data or infer system state from externally observable signals. Shielding must extend to internal buses and data pathways, not only to individual processing elements, as inter-component communications represent a significant and often overlooked emanations surface. The physical enclosure strategy must be integrated with the broader system architecture so that shielding effectiveness is not degraded by penetrations, connectors, or cable routing that create unintended emissions paths. During sustainment & maintenance, Spacecraft TEMPEST and EMSEC protections are primarily established during design, fabrication, and integration, but sustainment remains applicable through configuration control, review of deployment-state or hardware changes, preservation of qualification evidence, assessment of relevant anomalies, and evaluation of refurbishment, replacement, or follow-on production changes. The guidance below addresses these spacecraft considerations as well as applicable ground-segment maintenance activities. | PE-19 PE-19(1) PE-21 SC-8(3) | A.7.5 A.7.8 A.8.12 | ||||
| CM0050 | On-board Message Encryption | Authentication controls on the spacecraft internal bus verify the identity of communicating components but do not protect the confidentiality of the data in transit; an adversary with access to the bus, whether through a compromised component, a hardware implant, or a physical access event, can observe all unencrypted inter-component communications regardless of whether authentication is enforced. Encrypting data traversing the spacecraft internal bus protects the confidentiality of selected message content from entities that can observe the bus but do not possess authorization and the applicable cryptographic keys. The protection does not prevent disclosure to a compromised component that legitimately possesses the decryption key, and it may not conceal unencrypted protocol headers, addressing information, message timing, or traffic volume. Bus encryption should be considered for bus segments or message types carrying information whose unauthorized disclosure would create unacceptable mission, security, privacy, or operational risk. Criticality alone does not establish a confidentiality requirement. Where confidentiality is required, encryption must be combined with message integrity, source authentication, and replay protection through an approved authenticated-encryption mechanism or an appropriately composed set of cryptographic protections. | AC-4 AC-4(23) AC-4(24) AC-4(26) AC-4(31) AC-4(32) PL-8 PL-8(1) SA-3 SA-8 SA-8(18) SA-8(19) SA-8(9) SA-9(6) SC-13 SC-16 SC-16(1) SC-16(2) SC-16(3) SC-8(1) SC-8(3) SI-19(4) SI-4(10) SI-4(25) | A.5.14 A.8.22 A.8.23 A.8.11 A.5.8 A.5.2 A.5.8 A.8.25 A.8.31 A.8.27 A.8.28 A.5.33 A.8.24 A.8.26 A.5.31 A.8.11 | ||||
| CM0060 | Secret Shares | Secret sharing for side-channel protection, commonly implemented as masking, represents each sensitive value or intermediate computation using multiple randomized shares. A masking scheme of order dtypically uses d+1 shares and is designed so that observation of up to dshares or covered intermediate values does not reveal information about the underlying sensitive value within the defined security model. The complete set of shares reconstructs the original value and therefore must not be considered mutually independent. Computation must be performed on the shares using masking operations or gadgets designed to preserve the required security order. Masking can prevent straightforward first-order exploitation and increase the observations or attack complexity required to recover the secret, but joint leakage from multiple shares, unintended recombination, register transitions, glitches, memory activity, or other implementation effects may remain exploitable. Higher-order attacks specifically attempt to combine leakage associated with multiple shares and are not eliminated merely by dividing a value into shares. The primary operational tradeoff is a significant increase in computational operations, approaching a doubling of the number of operations required, which translates directly into increased power consumption; this overhead must be evaluated carefully against the spacecraft's power budget and the processing constraints of the target hardware. Masking should be applied to the complete set of operations, intermediate values, key schedules, conversions, memory transfers, and control paths whose leakage could disclose the protected secret. Selective masking may be used when analysis demonstrates that unmasked operations and transitions do not expose secret-dependent information and that the resulting implementation remains secure within the approved leakage model. | PE-19 PE-19(1) | A.7.5 A.7.8 A.8.12 | ||||
| CM0061 | Power Masking | Power masking is a side-channel countermeasure in which secret-dependent values and intermediate computations are represented using multiple randomized shares. A masking scheme of order d is designed so that observations involving up to dcovered intermediate values do not reveal information about the protected secret under the scheme’s defined leakage and adversary model. Correctly implemented masking can prevent straightforward lower-order exploitation and increase the complexity or number of observations required for successful power or electromagnetic analysis. It does not guarantee protection regardless of the number of measurements: higher-order, profiled, multivariate, or implementation-specific attacks may combine leakage from multiple shares or observations and recover the protected secret. The masking scheme generates randomized shares and performs the protected computation using masking operations designed to preserve the required security order. Reconstruction or conversion to an unmasked representation must occur only at an explicitly authorized boundary and must not expose secret-dependent values through registers, memory, buses, transitions, glitches, control flow, or other observable implementation state. Power masking applies secret-sharing principles to the secret key, cryptographic state, and other secret-dependent intermediate values throughout a computation. CM0060 may describe the general share-based protection concept, while CM0061 should focus on implementing and preserving that sharing across cryptographic operations to reduce exploitable power and electromagnetic leakage. Effective masking requires correct implementation across the entire cryptographic execution path, as a single unmasked intermediate value anywhere in the computation can restore exploitable correlation and defeat the protection. | PE-19 PE-19(1) | A.7.5 A.7.8 A.8.12 | ||||