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Power Consumption Obfuscation

Power consumption obfuscation encompasses hardware circuit design techniques and architectural obfuscation strategies that mask the relationship between a device's internal operations and its observable power consumption profile, increasing the difficulty and cost of power analysis side-channel attacks. Unlike power randomization, which adds noise to the power signal, obfuscation techniques actively obscure the underlying power consumption pattern through circuit-level design approaches such as dual-rail logic, balanced circuit topologies, and constant-power execution paths that decouple observable power draw from data-dependent computational activity. These techniques increase manufacturing cost and design complexity for sensor nodes and other embedded hardware, representing a one-time investment at fabrication that must be justified against the mission's physical threat environment and the sensitivity of the data processed by the protected device. Power consumption obfuscation is most effectively applied to hardware executing cryptographic operations or other security-sensitive functions where correlation between power traces and internal state would be most damaging if successfully exploited.

Sources

  • Y. Ishai, M. Prabhakaran, A. Sahai, and D. Wagner. Private circuits 2: Keeping secrets in tamperable circuits. In Proceedings of Eurocrypt, pages 308– 327, May 2006.
  • Y. Ishai, A. Sahai, and D. Wagner. Private circuits: Securing hardware against probing attacks. In Proceedings of CRYPTO, pages 463–481, 2003.
  • P. C. Kocher, J. Jaffe, and B. Jun. Differential power analysis. In CRYPTO, pages 388–397, 1999
ID: CM0059
Tier: III
Onboard SV CM 
Created: 2022/10/19
Last Modified: 2026/08/06

Pre-Operations Government

Acquisition requirements should address power analysis side-channel resistance as a security design requirement for hardware components executing cryptographic or security-critical functions, identifying power consumption obfuscation as a candidate implementation approach alongside complementary techniques, with selection governed by a documented trade analysis that accounts for manufacturing cost, design complexity, and the mission's threat environment. Requirements should define the applicable side-channel threat model and evaluation objectives, including adversary access, measurement and profiling capability, observation budget, target operations, protected secrets, operating conditions, and relevant power or electromagnetic leakage channels. Acceptance criteria should use approved quantitative leakage or attack-success measures rather than relying solely on general claims of simple power analysis (SPA) or differential power analysis (DPA) resistance. Contract language should require that obfuscation techniques applied to security-critical hardware be documented as controlled design attributes with their manufacturing cost impact quantified and incorporated into the program's hardware cost baseline. Evaluation criteria should assess offerors' proposed obfuscation approach, the rigor of their side-channel evaluation methodology, and their experience implementing power consumption obfuscation in space-grade or similarly constrained embedded hardware. Verification should include side-channel testing using power trace acquisition and statistical analysis on production samples, confirming that the obfuscation achieves the specified resistance level against the attack techniques identified in the mission's threat model. Testing should combine statistical leakage assessment with threat-relevant attack testing where appropriate and must document measurement sensitivity, trace counts, device variation, detected leakage, attack outcomes, coverage limitations, and residual risk.

Pre-Operations Developer/Supplier

Power consumption obfuscation techniques must be selected and integrated during the chip or circuit design phase, before layout is finalized, as obfuscation approaches such as dual-rail logic or balanced circuit topologies require fundamental changes to gate-level design that cannot be added after the design is committed to fabrication. The selection among obfuscation techniques should be based on a quantitative security and resource trade, comparing the side-channel resistance achieved by each approach against its impact on circuit area, power overhead, timing margins, and manufacturing cost, with the analysis documented as part of the hardware security design record. Dual-rail, precharge, balanced, or other hiding-oriented circuit techniques should be considered where they provide meaningful resistance under the applicable implementation and threat model. Their effectiveness depends on physical balance, glitch behavior, routing, control logic, and surrounding circuitry, and their area, timing, and power overhead must be measured for the specific design. Selective implementation may reduce resource impact but must cover all operations and data paths whose leakage could reveal the protected secret. Verification should include pre-silicon analysis at the appropriate logical, gate, and post-layout levels to identify likely leakage and implementation imbalance. Final assurance must include post-silicon side-channel evaluation of production-representative devices because simulation may not fully represent parasitic effects, routing imbalance, process variation, packaging, power distribution, environmental conditions, and measurement-access characteristics. The manufacturing cost increment associated with obfuscated hardware should be captured in the program's cost model from the component selection phase, ensuring that the cost of physical side-channel protection is visible in program budgets rather than discovered as a surprise during procurement.