Increase Clock Cycles/Timing

Use more clock cycles such that branching does not affect the execution time. Also, the memory access times should be standardized to be the same over all accesses. If timing is not mission critical and time is in abundance, the access times can be reduced by adding sufficient delay to normalize the access times. These countermeasures will result in increased power consumption which may not be conducive for low size, weight, and power missions.

Sources

NIST Rev5 Controls

D3FEND Techniques

D3FEND Artifacts

None

ISO 27001

NASA Best Practice Guide

ESA Space Shield Mitigation

Related MITRE EMB3D Mitigations

Related CSF 2.0

Related BSI Security Measures

ID: CM0063
Tier: III
Onboard SV CM 
Created: 2022/10/19
Last Modified: 2023/10/17