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Secret Shares

Secret sharing for side-channel protection, commonly implemented as masking, represents each sensitive value or intermediate computation using multiple randomized shares. A masking scheme of order dtypically uses d+1 shares and is designed so that observation of up to dshares or covered intermediate values does not reveal information about the underlying sensitive value within the defined security model. The complete set of shares reconstructs the original value and therefore must not be considered mutually independent. Computation must be performed on the shares using masking operations or gadgets designed to preserve the required security order. Masking can prevent straightforward first-order exploitation and increase the observations or attack complexity required to recover the secret, but joint leakage from multiple shares, unintended recombination, register transitions, glitches, memory activity, or other implementation effects may remain exploitable. Higher-order attacks specifically attempt to combine leakage associated with multiple shares and are not eliminated merely by dividing a value into shares. The primary operational tradeoff is a significant increase in computational operations, approaching a doubling of the number of operations required, which translates directly into increased power consumption; this overhead must be evaluated carefully against the spacecraft's power budget and the processing constraints of the target hardware. Masking should be applied to the complete set of operations, intermediate values, key schedules, conversions, memory transfers, and control paths whose leakage could disclose the protected secret. Selective masking may be used when analysis demonstrates that unmasked operations and transitions do not expose secret-dependent information and that the resulting implementation remains secure within the approved leakage model.

Sources

  • L. Goubin and J. Patarin. DES and differential power analysis (the duplication method). In Cryptographic Hardware and Embedded Systems, pages 158–172, 1999.
ID: CM0060
Tier: II
Onboard SV CM 
Created: 2022/10/19
Last Modified: 2026/08/06

Pre-Operations Government

Acquisition requirements should address side-channel resistance for hardware and software executing cryptographic operations, identifying secret sharing as a candidate countermeasure alongside hardware-level alternatives, with selection governed by a documented trade analysis that weighs cryptographic protection effectiveness against power and computational overhead for each application context. Requirements should specify the target level of side-channel resistance in terms of resistance to first-order and higher-order DPA attacks, and should require that the implemented secret sharing scheme's security properties be validated through both theoretical analysis and empirical side-channel evaluation on representative hardware. Contract language should require that the power consumption impact of secret sharing implementations be quantified and incorporated into the system power budget, ensuring that the overhead is visible in resource planning rather than discovered during integration. Evaluation criteria should assess offerors' proposed secret sharing implementation, their masking order and the corresponding security level achieved, and their experience implementing share-based countermeasures in resource-constrained embedded environments. Verification should include side-channel evaluation testing on production-representative hardware, confirming that the implementation achieves the specified resistance to DPA attacks and that no first-order or higher-order leakage remains detectable above the defined assurance threshold.

Pre-Operations Developer/Supplier

Secret sharing implementation must be designed and validated at the algorithm and software level before integration into flight hardware, as the security properties of a share-based implementation depend critically on the correctness of the probabilistic share generation, the independence of share-based computations, and the absence of unintended recombination points that would restore the original value in a power-observable context. A masking scheme of order dcommonly represents each sensitive value using d+1 shares and is intended to resist attacks combining up to d covered leakages under its defined security model. Increasing the order can raise the complexity of higher-order attacks, but practical security also depends on noise, share independence, refreshing, leakage from multiple intermediate values, physical implementation, and the attacker’s profiling capability. Overhead does not scale uniformly: linear operations may scale approximately with the number of shares, while nonlinear operations and secure masking gadgets may scale quadratically or otherwise according to the scheme. Resource-budget analysis must account for the measured execution-time, memory, code-size, randomness-generation, power, thermal, and scheduling overhead of the selected masking implementation across applicable operational modes and worst-case concurrent workloads. Random number generation quality is a foundational dependency of secret sharing security; the share generation process must use a cryptographically secure random source with sufficient entropy to ensure that shares are genuinely statistically independent, as weak randomness can reduce secret sharing to an ineffective countermeasure regardless of implementation correctness. Side-channel evaluation should be conducted at multiple abstraction levels, including both algorithmic simulation and physical measurement on fabricated hardware, to confirm that the implementation achieves the intended security properties in the actual execution environment.